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AS4LC2M8S1-12TC Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS4LC2M8S1-12TC Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 28 page 2 ALLIANCE SEMICONDUCTOR 7/5/00 AS4LC2M8S1 AS4LC1M16S1 Functional description The AS4LC2M8S1 and AS4LC1M16S1 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288 words × 16 bits × 2 banks (2048 rows × 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data (512 bytes for 2M × 8 and 256 bytes for 1M × 16) without selecting a new column address. The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation; and (3) the capability to change column-address randomly on every clock cycle during burst access. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. SDRAM commands and functions are decoded from control inputs. Basic commands are as follows: Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1 has 44 pins, and the AS4LC1M16S1 has 50 pins. Both devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL compatible. Logic block diagram † For AS4LC2M8S1, Banks A and B will read 1M × 8 (2048 × 512 × 8). • Mode register set • Deactivate bank • Deactivate all banks • Select row; activate bank • Select column; write • Select column; read • Deselect; power down • CBR refresh • Auto precharge with read/write • Self-refresh RAS CAS WE CLK CKE Clock generator Mode register Row address buffer Refresh counter Column address buffer Burst counter Sense amplifier Column decoder and latch circuit Data control circuit DQ DQMU/DQML CS Bank select A11 Bank B† Bank A† 512K × 16 (2048 × 256 × 16) 512K × 16 (2048 × 256 × 16) A[10:0] |
Similar Part No. - AS4LC2M8S1-12TC |
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Similar Description - AS4LC2M8S1-12TC |
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