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ISPLSI2032A-80LT48 Datasheet(PDF) 11 Page - Lattice Semiconductor |
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ISPLSI2032A-80LT48 Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 15 page Specifications ispLSI 2032/A 11 Pin Description 1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability. Input/Output Pins — These are the general purpose I/O pins used by the logic array. NAME Table 2-0002A-08isp/2032 44-PIN PLCC PIN NUMBERS DESCRIPTION 15, 19, 25, 29, 37, 41, 3, 7, 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 18, 22, 28, 32, 40, 44, 6, 10 Global Output Enable input pin. 2 GOE 0 1, 23 GND VCC 12, 34 17, 39 6, 28 18, 42 6, 30 VCC No Connect. 12, 24, 36, 48 NC1 Ground (GND) Input — This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN0 also is used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: Input — Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. RESET/Y1 Y0 SDI/IN 02 ispEN MODE Input — When in ISP Mode, controls operation of ISP state machine. - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Output/Input — This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. SDO/IN 12 Input — This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can be routed to any GLB and/or I/O cell on the device. SCLK/Y22 - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. 35 11 14 13 36 24 33 44-PIN TQFP PIN NUMBERS 48-PIN TQFP PIN NUMBERS 9, 13, 19, 23, 31 35, 41, 1, 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 40 5 29 7 8 30 18 27 9, 14, 20, 25, 33, 38, 44, 1, 10, 15, 21, 26, 34, 39, 45, 2, 11, 16, 22, 27, 35, 40, 46, 3, 13, 17, 23, 28, 37, 41, 47, 4 43 5 31 7 8 32 19 29 |
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