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PRELIMINARY
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Document Number: 38-05621 Rev. **
Page 3 of 24
1M x 18 Array
Write
Reg
Write
Reg
Logic Block Diagram (CY7C1318BV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS[1:0]
VREF
18
20
C
C
18
LD
Control
Burst
Logic
A0
A(19:1)
19
CQ
CQ
R/W
DOFF
Logic Block Diagram (CY7C1320BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS[3:0]
VREF
36
19
C
C
36
LD
Control
Burst
Logic
A0
A(18:1)
18
512K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
R/W
DOFF