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XRT7295AE Datasheet(PDF) 3 Page - Exar Corporation |
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XRT7295AE Datasheet(HTML) 3 Page - Exar Corporation |
3 / 18 page XRT7295AE 3 Rev.1.20 PIN CONFIGURATION VDDA LOSTHR REQB ICT GNDA RIN TMC1 LPF1 RPDATA RNDATA RCLK EXCLK LPF2 TMC2 RLOS RLOL VDDC GNDD VDDD GNDC 20 Lead SOJ (Jedec, 0.300”) 20 1 11 10 2 3 4 5 6 7 15 14 13 12 17 16 8 9 19 18 PIN DESCRIPTION Pin # Symbol Type Description 1 GNDA Analog Ground. 2 RIN I Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series with 50 kW. 3,6 TMC1-TMC2 I Test Mode Control 1 and 2 . Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. 4,5 LPF1-LPF2 I PLL Filter 1 and 2 . An external capacitor (0.1mF ±20%) is connected between these pins. 7 RLOS O Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input. (See Table 6) 8 RLOL O Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock. 9 GNDD Digital Ground for PLL Clock . Ground lead for all circuitry running synchronously with PLL clock. 10 GNDC Digital Ground for EXCLK . Ground lead for all circuitry running synchronously with EXCLK. 11 VDDD 5V Digital Supply (±10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 12 VDDC 5V Digital Supply (±10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. 13 EXCLK I External Reference Clock . A valid DS3 (44.736MHz ±100ppm) or STS-1 (51.84MHz + 100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD /2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns. 14 RCLK O Receive Clock . Recovered clock signal to the terminal equipment. 15 RNDATA O Receive Negative Data . Negative pulse data output to the terminal equipment. (See Figure 11. ) 16 RPDATA O Receive Positive Data . Positive pulse data output to the terminal equipment. (See Figure 11 ) 17 ICT I In-circuit Test Control (Active-low) . If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir- cuit testing. There is an internal pull-up on this pin. 18 REQB I Receive Equalization Bypass . A high on this pin bypasses the internal equalizer. A low places the equalizer in the data path. 19 LOSTHR I Loss-of-signal Threshold Control . The voltage forced on this pin controls the input loss- of-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin must be set to the desired level upon power-up and should not be changed during opera- tion. 20 VDDA 5V Analog Supply (±10%). |
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