HT48CA6

Rev. 1.10

6

July 26, 2002

All data memory areas can handle arithmetic, logic, in-

crement, decrement and rotate operations directly. Ex-

cept for some dedicated bits, each bit in the data

memory can be set and reset by the SET [m].i and CLR

[m].i instructions, respectively. They are also indirectly

accessible through memory pointer register (MP;01H).

Indirect addressing register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation of

[00H] accesses data memory pointed to by MP (01H).

Reading location 00H itself indirectly will return the re-

sult 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 6-bit regis-

ter. The bit 7~6 of MP is undefined and reading will re-

turn the result

²1². Any writing operation to MP will only

transfer the lower 6-bit data to MP.

Accumulator

The accumulator closely relates to ALU operations. It is

also mapped to location 05H of the data memory and is

capable of carrying out immediate data operations.

Data movement between two data memory locations

has to pass through the accumulator.

Arithmetic and logic unit

- ALU

This circuit performs 8-bit arithmetic and logic opera-

tion. The ALU provides the following functions.

SBC, DAA)

The ALU not only saves the results of a data operation but

also changes the contents of the status register.

Status register

- STATUS

This 8-bit status register (0AH) contains the 0 flag (Z),

carry flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PD) and watchdog time-out flag (TO). It

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 3 2 B y t e s )

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 . H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 . H

3 . H

I n d i r e c t A d d r e s s i n g R e g i s t e r

M P

A C C

P C L

T B L P

T B L H

S T A T U S

P A

P B

P C

: U n u s e d

R e a d a s " 0 0 "

2 0 H

RAM mapping

Labels

Bits

Function

C0

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

AC

1

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z

2

Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.

OV

3

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PD

4

PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set

by executing the HALT instruction.

TO

5

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set

by a WDT time-out.

¾

6

Unused bit, read as

²0²

¾

7

Unused bit, read as

²0²

Status register