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P80CL410HFT Datasheet(PDF) 9 Page - NXP Semiconductors |
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P80CL410HFT Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 28 page Philips Semiconductors Product specification 80CL410/83CL410 Low voltage/low power single-chip 8-bit microcontroller with I2C 1995 Jan 20 9 76 5 4 3 2 1 0 S1CON 76 5 4 3 2 1 0 S1STA BUS CLOCK GENERATOR Figure 3. Serial I/O ARBITRATION LOGIC SHIFT REGISTER S1DAT SLAVE ADDRESS S1ADR GC SDA SCL I2C-BUS SERIAL I/O The serial port supports the twin line I2C-bus. The I2C-bus consists of a data line (SDA) and a clock line (SCL). These lines also function as I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in four modes: – Master transmitter – Master receiver – Slave transmitter – Slave receiver These functions are controlled by the S1CON register. S1STA is the status register whose contents may also be used as a vector to various service routines. S1DAT is the data shift register and S1ADR the slave address register. Slave address recognition is performed by hardware. S1CON (D8H) Serial control register CR2 ENS1 STA STO SI AA CR1 CR0 CR0, CR1, CR2 These three bits determine the serial clock frequency when SIO is in a master mode. AA Assert acknowledge bit. When the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: – own slave address is received – general call address is received (S1ADR.0 = 1) – data byte received while device is programmed as master – data byte received while device is selected slave With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested when the “own slave address” or general call address is received. SI SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of the following conditions: – a start condition is generated in master mode – own slave address received during AA = 1 – general call address received while S1ADR.0 and AA = 1 – data byte received or transmitted in master mode (even if arbitration is lost) – data byte received or transmitted as selected slave – stop or start condition received as selected slave receiver or transmitter STO STOP flag. With this bit set while in master mode, a STOP condition is generated. When a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the slave mode, the STO flag may also be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases SDA and SCL. The SIO then switches to the “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware. STA START flag. When the STA bit is set in slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If STA is set while the SIO is in master mode, SIO transmits a repeated START condition. ENS1 When ENS1 = 0, the SIO is disabled. The SDA and SCL outputs are in a high-impedance state; P1.6 and P1.7 function as open drain ports. When ENS1 = 1, the SIO is enabled. The P1.6 and P1.7 port latches must be set to logic 1. |
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