P83CL410HFP datasheet(8/28 Pages) PHILIPS

Part #	P83CL410HFP

Description	Low voltage/low power single-chip 8-bit microcontroller with I2C

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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Philips Semiconductors

Product specification

80CL410/83CL410

Low voltage/low power single-chip

8-bit microcontroller with I2C

1995 Jan 20

8

POWER-DOWN MODE

The instruction setting PCON.1 is the last

executed prior to going into the power-down

mode. In power-down mode, the oscillator is

stopped. The contents of the the on-chip

RAM and SFRs are preserved. The port pins

output the values held by their respective

SFRs. ALE and PSEN are held low.

In the power-down mode, VDD may be

reduced to minimize power consumption.

However, the supply voltage must not be

reduced until the power-down mode is active,

and must be restored before the hardware

reset is applied and frees the oscillator. Reset

must be held active until the oscillator has

restarted and stabilized.

From the power-down mode the part can be

restarted by using either the wake-up mode

or the Reset Mode.

Wake-Up Mode

Setting both PD and IDL bits in the PCON

register forces the controller into the

power-down mode. Setting both bits enable

the controller to be woken-up from the

power-down mode via either an enabled

external interrupt INT2–INT9, or a reset

operation.

An external interrupt for an enabled interrupt

INT2–INT9 at port 1 starts both the oscillator

and the delay counter. To ensure that the

oscillator is stable before the controller

restarts, the internal clock will remain inactive

for 1536 oscillator periods after the interrupt

is detected. This is controlled by the on-chip

delay counter. After this, the PD flag will be

reset, the controller is now in the Idle mode

and the interrupt will be handled in the normal

way.

Reset Mode

Setting only the PD bit in the PCON register

again forces the controller into the

power-down mode, but in this case it can

only be restored to normal operation with a

direct reset operation.

To restore normal operation, the RESET pin

has to be kept High for a minimum of 24

oscillator periods. The on-chip delay counter

is inactive. The user has to insure that the

oscillator is stable before any operation is

attempted. Figure 2 illustrates the two

possibilities for wake-up.

IDLE MODE

The instruction that sets PCON.0 is the last

instruction executed before going into idle

mode. In idle mode, the internal clock is

stopped for the CPU, but not for the interrupt,

timer, and serial port functions. The CPU

status is preserved along with the stack

pointer, program counter, program status

word and accumulator. The RAM and all

other registers maintain their data during idle

mode. The port pins retain the logical states

they held at idle mode activation. ALE and

PSEN hold at the logic high level.

There are two methods used to terminate the

idle mode. Activation of any interrupt will

cause PCON to be cleared by hardware;

terminating idle mode. The interrupt is

serviced, and following the instruction RETI,

the next instruction to be executed will be the

one following the instruction that put the

device in the the idle mode.

Flag bits GF0 and GF1 can be used to

determine whether the interrupt was received

during normal execution or idle mode. For

example, the instruction that writes to

PCON.0 can also set or clear one or both flag

bits. When idle mode is terminated by an

interrupt, the service routine can examine the

status of the flag bits.

The second method of terminating the idle

mode is with an external hardware reset.

Since the oscillator is still running, the

hardware reset is required to be active for

only two machine cycles to complete the

reset operation. Reset redefines all SFRs,

but does not affect the state of the on-chip

RAM.

The status of the external pins during idle and

power-down mode is shown in Table 2. If the

power-down mode is activated while

accessing external memory, port data held in

the special function register P2 is restored to

port 2. If the data is a logic 1, the port pin is

held high during the power-down mode.

Table 2.

External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

1

Data

Idle

External

1

Floating

Data

Address

Data

Power-down

Internal

0

Data

Power-down

External

0

Floating

Data

Figure 2. Wake-Up Operation

> 24 PERIODS

DELAY COUNTER

1536 PERIODS

POWER-DOWN

RESET PIN

EXTERNAL INTERRUPT

OSCILLATOR

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