AIC111

SLAS382 – JUNE 2003

www.ti.com

2

Thesedevices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

The AIC111 comes in a 32-pin QFN 5

×5-mm package. A 32-pad solder ball bumped flip chip die that comes in waffle

packs or tape and reel is in preview and will be available 3rd quarter 2003.

AVAILABLE OPTIONS

PART NUMBER

PACKAGE

AIC111RHB

32-pin QFN (5 mm x 5 mm), in tube.

AIC111RHBR

32-pin QFN (5 mm x 5 mm), tape and reel

AIC111YE

32-pad waffle scale chip package, bumped die in waffle pack (contact the factory for availability) – Preview,

available 3rd quarter 2003

AIC111YER

32-pad (WSCP) bumped die in tape and reel (contact the factory for availability) – Preview, available 3rd

quarter 2003

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)(2)

UNIT

Input voltage

AI or DI pins

–0.3 V to 4 V

Power supply

VDD, power pins

–0.3 V to 4.5 V

Latch-up tolerance

JEDEC latch-up (EIA/JEDS78)

100 mA

Operating free-air temperature range, TA

0

°C to 70°C

Functional temperature range

–15

°C to 85°C

Reflow temperature range (flip chip)

220

°C to 230°C

Storage temperature range, Tstg

–40

°C to 125°C

Storage humidity

65% R.H.

(1) Stresses beyond those listed under absolutemaximumratings may cause permanent damage to the device. These are stress ratings only, and

functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperatingconditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.

ELECTRICAL CHARACTERISTICS

INPUT/OUTPUT, OPERATING TEMPERATURE AT 25

°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Digital interface (see Notes 1 and 2)

BUF_DVDD (see Note 1)

3.6

V

VIH High-level input voltage

BUF_DVDD–0.2

V

VIL Low-level input voltage

BUF_DVSS+0.2

V

VOH High-level output voltage

BUF_DVDD

V

VOL Low-level output voltage

BUF_DVSS

V

Maximum allowed input voltage (AVIN)

Differential

450

mVpk

Input impedance (AVIN) (see Note 3)

Nominal gain = 50x

20

k

Ω

Input capacitance (AVIN)

5

pF

Microphone bias voltage (MIC_VSUP)

20-

µA maximum

0.87

0.94

0.99

V

Microphone bias resistor (MIC_BIAS)

27

29.1

31

k

Ω

H bridge amplifier output

DAC full scale output differential

Fixed Q

3/4 HB_VDD

V

H-bridge amplifier output

DAC full scale output differential

Adaptive Q

HB_VDD

VPP

Output resistance

Differential, HB – VDD = 1.3 V

20 or 40

Ω

(1) DVDD, VDD_OSC, and AVDD should be within 50 mV, preferably connected together.

AVSS1, 2, DVSS, and VSS_OSC should be within 50 mV, preferably connected together.

(2) Maximum (0.9 V, DVDD –0.5 V)

≤ BUF_DVDD ≤3.6 V

(3) Driving single-ended: Rin = R

× [(1+A)/(2+A)], A = PGAC Gain (linear), R = 20.4 kΩ for A ≥ 4 or 20.4 kΩ × (4/A) for A<4.

Rin(min) = 17 k

Ω (A=4), Rin(max) = 59.89 kΩ (A = 0.89), Rin(nom) = 20 kΩ (A = 50).