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8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L512L18F_2.p65 – Rev. 7/00

©2000, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

FLOW-THROUGH SYNCBURST SRAM

SRAM

FEATURES

• Fast clock and OE# access times

• Separate +3.3V or +2.5V isolated output buffer

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion

and address pipelining

• Clock-controlled and registered addresses, data I/

Os and control signals

• Internally self-timed WRITE cycle

• Burst control (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-pin TQFP package

• 165-pin FBGA

• Low capacitive bus loading

• x18, x32, and x36 versions available

OPTIONS

MARKING*

• Timing (Access/Cycle/MHz)

7.5ns/8.8ns/113 MHz

-7.5

8.5ns/10ns/100 MHz

-8.5

10ns/15ns/66 MHz

-10

• Configurations

3.3V I/O

512K x 18

MT58L512L18F

256K x 32

MT58L256L32F

256K x 36

MT58L256L36F

2.5V I/O

512K x 18

MT58L512V18F

256K x 32

MT58L256V32F

256K x 36

MT58L256V36F

• Packages

100-pin TQFP (2-chip enable)

T

100-pin TQFP (3-chip enable)

S

165-pin, 13mm x 15mm FBGA

F

• Operating Temperature Range

Commercial (0°C to +70°C)

None

Part Number Example:

MT58L256V36FT-10

* A Part Marking Guide for the FBGA devices can be found on Micron's

web site—http://www.micronsemi.com/support/index.html.

MT58L512L18F, MT58L256L32F,

MT58L256L36F; MT58L512V18F,

MT58L256V32F, MT58L256V36F

*JEDEC-standard MS-026 BHA (LQFP).

100-Pin TQFP*

165-Pin FBGA

(Preliminary Package Data)

GENERAL DESCRIPTION

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 8Mb SyncBurst SRAMs integrate a 512K x

18, 256K x 32, or 256K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock in-

put (CLK). The synchronous inputs include all ad-

dresses, all data inputs, active LOW chip enable (CE#),

two additional chip enables for easy depth expansion

(CE2#, CE2), burst control inputs (ADSC#, ADSP#,