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MX10E80501 Datasheet(PDF) 5 Page - Macronix International |
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MX10E80501 Datasheet(HTML) 5 Page - Macronix International |
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5 / 88 page  5 P/N:PM0887 MX10E8050I / Specifications subject to change without notice, contact your sales representatives for the most update information. PRELIMINARY MX10E8050IA REV. 1.6, MAR. 28, 2005 13-19 7-13 pull-ups. Port 3 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of MX10E8050I family, as listed below: 10 11 5 I RxD (P3.0) : Serial input port 11 13 7 O TxD (P3.1) : Serial output port 12 14 8 I INT0 (P3.2) : External interrupt 0 13 15 9 I INT1 (P3.3) : External interrupt 1 14 16 10 I T0 (P3.4) : Timer 0 external input 15 17 11 I T1 (P3.5) : Timer 1 external input 16 18 12 O WR (P3.6) : External data memory write strobe 17 19 14 O RD (P3.7) : External data memory read strobe P4.0~P4.3 I/O Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. As inputs, Port 4 pins that are externally pulled low will source current because of the internal pull-ups. Port 4 also serves the special features of MX10E8050I family, as listed below: P4.0 23 17 I PWM0 (P4.0) : PWM module output 0 P4.1 34 28 I PWM1 (P4.1) : PWM module output 1 P4.2 1 39 I PWM2 (P4.2) : PWM module output 2 P4.3 12 6 I PWM3 (P4.3) : PWM module output 3 RST 9 10 4 I Reset : A high on this pin for eight machine cycles while the oscillator is running, reset the devices. ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at constant rate of 1/6 the oscillator frequency in 12x clock mode. 1/3 the oscillator frequency in 6x clock mode, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program memory. When executing code from external program memory, PSEN is activated twice each machine cycle., except the two PSEN activation are skipped during each access to external data memory. PSEN is not activated during fetch from internal program memory. EA 31 35 15 I External Access Enable/ Programming Supply Voltage: EA must be external held low to enable the device to fetch code from external program memory locations 0000H and FFFFH for 64 K devices. XTAL 1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL 2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. |
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