Power Supply

The MAX1363 (2.7V to 3.6V) and MAX1364 (4.5V to

5.5V) operate from a single supply and consume

670µA (typ) at sampling rates up to 94.4ksps and

436µA in monitor mode at 133ksps. The MAX1363

features a 2.048V internal reference, and the MAX1364

features a 4.096V internal reference. All devices can be

configured for use with an external reference from 1V to

ceramic capacitor for best performance.

Analog-Input and Track/Hold

The MAX1363/MAX1364 analog-input architecture con-

tains an analog-input multiplexer (mux), fully differential

T/H, comparator, and a fully differential switched

capacitive digital-to-analog converter (DAC). Figure 3

shows the equivalent input circuit for the MAX1363/

MAX1364.

In single-ended mode, the analog-input mux connects

GND (see the Configuration/Setup Bytes (Write Cycle)

section). In differential mode, the analog-input mux

selected by CS[3:0].

During the acquisition interval, the T/H switches are in

signal. At the end of the acquisition interval, the T/H

switches move to the hold position, retaining the

During the conversion, a switched capacitive DAC

adjusts to restore the comparator input voltage to 0V

within the limits of 12-bit resolution. This action requires

12 conversion clock cycles and is equivalent to trans-

binary-weighted capacitive DAC, forming a digital rep-

resentation of the analog-input signal.

Use a low source impedance to ensure an accurate

sample. A source impedance of up to 1.5k

Ω does not

significantly degrade sampling accuracy. For larger

source impedances, connect a 100pF capacitor from

the analog input to GND or buffer the input.

In internal clock mode, the T/H circuitry enters track

mode on the eighth rising clock edge of the address

byte (see the Slave Address section). The T/H circuitry

enters hold mode on the falling clock edge of the

acknowledge bit of the address byte (the ninth clock

pulse). The conversions are then internally clocked, dur-

ing which time the MAX1363/MAX1364 hold SCL low.

In external clock mode, the T/H circuitry enters track

mode after a valid address on the rising edge of the

clock during the read bit (R/W = 1). Hold mode is

entered on the rising edge of the second clock pulse

during the shifting out of the 1st byte of the result. The

next 12 clock cycles perform the conversions.

The time required for the T/H circuitry to acquire an

input signal is a function of the input sample capaci-

tance. If the analog-input source impedance is high,

the acquisition time constant lengthens and more time

must be allowed between conversions. The acquisition

to be acquired. It is calculated by:

4-Channel, 12-Bit System Monitors with Programmable

Trip Window and SMBus Alert Response

10

______________________________________________________________________________________

TRACK

AIN0

AIN1

AIN2

AIN3/REF

GND

ANALOG-INPUT MUX

CAPACITIVE

DAC

REF

CAPACITIVE

DAC

REF

MAX1363

MAX1364

HOLD

TRACK

HOLD

Figure 3. Equivalent Input Circuit