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TI380C30A Datasheet(PDF) 4 Page - Texas Instruments |
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TI380C30A Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 81 page  TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description The TI380C30A is a single-chip token-ring solution, combining the commprocessor and the physical-layer (PHY) interface onto a single device. The TI380C30A supports 16 Mbit/s and 4 Mbit/s of operation, conforms to ISO 8802–5/IEEE Std 802.5–1992 standards, and has been verified to be completely IBM Token-Ring Network compatible. The TI380C30A provides a high degree of integration as it combines the functions of the TI380C25 and the TI380C60A onto a single chip. Additional information on the PHY section can be found in the TI380C60A data sheet, literature number SPWS033. With the TI380C30A, only local memory and minimal additional components such as PAL® devices and crystal oscillators need to be added to complete the LAN-subsystem design. The TI380C30A provides a 32-bit system-memory address reach with a high-speed bus-master direct memory access (DMA) interface that supports rapid communications with the host system. In addition, the TI380C30A supports direct I/O and a low-cost 8-bit or 16-bit pseudo-DMA interface that requires only a chip-select to work directly on an 80x8x 8-bit slave I/O interface. Selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility. The TI380C30A supports addressing for up to 2M bytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or database transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host. The proprietary central processing unit (CPU) used in the TI380C30A allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols [such as logical link control (LLC)] to the LAN-subsystem, overall system performance is increased. This is accomplished by offloading processing from the host-system to the TI380C30A, which also can reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance is possible. The TI380C30A includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries and burst size, and track host- and LAN-subsystem-buffer status. Previously, these counters were maintained in software. By integrating them into hardware, software overhead is reduced and LAN-subsystem performance is improved. The TI380C30A implements a Texas Instruments (TI ™)-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C30A has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture. At the PHY, the Manchester-encoded data stream is received and phase-aligned using an on-chip dual-digital phase-locked loop (PLL). Both the recovered clock and data are passed to the protocol-handling circuits on the TI380C30A for serial-to-parallel conversion and data processing. On transmit, the TI380C30A buffers the output from the protocol-handling circuit and drives the media by way of suitable isolation and waveform-shaping components. The TI380C30A uses CMOS technology to reduce power consumption to PCMCIA-compatible levels. Power-management features are incorporated to support Green PC compatibility. In addition to the PLL, all other functions required to interface to an IEEE Std 802.5 token ring are provided. These functions include the phantom drive to control the relays within a trunk-coupling unit and wire-fault detection circuits; an internal-wrap function for self-test; and a watchdog timer to provide fail-safe deinsertion from the ring in the event of a station, microcode, or commprocessor failure. |
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