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K7N323645M-FC25 Datasheet(PDF) 3 Page - Samsung semiconductor

Part # K7N323645M-FC25
Description  1Mx36 & 2Mx18 Pipelined NtRAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

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K7N323645M
1Mx36 & 2Mx18 Pipelined NtRAMTM
- 3 -
Rev 2.0
Nov. 2003
K7N321845M
1Mx36 & 2Mx18-Bit Pipelined NtRAMTM
The K7N323645M and K7N321845M are 37,748,736-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N323645M and K7N321845M are implemented with
SAMSUNG
′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins
minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
• 2.5V
±5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A.
• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
FAST ACCESS TIMES
PARAMETER
Symbol
-25
-20
-16
-13
Unit
Cycle Time
tCYC
4.0
5.0
6.0
7.5
ns
Clock Access Time
tCD
2.6
3.2
3.5
4.2
ns
Output Enable Access Time
tOE
2.6
3.2
3.5
4.2
ns
NtRAM TM and No Turnaround Random Access Memory are trademarks of Samsung.
LOGIC BLOCK DIAGRAM
WE
BWx
CLK
CKE
CS1
CS2
CS2
ADV
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
ADDRESS
ADDRESS
REGISTER
A
0~A′1
36 or 18
DQPa ~ DQPd
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
K
A [0:19]or
A [0:20]
LBO
A2~A 19 or A 2~A 20
A 0~A 1
(x=a,b,c,d or a,b)
1Mx36, 2Mx18
MEMORY
ARRAY


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