Micro Networks

324 Clark Street

Worcester, MA 01606

tel: 508-852-5400

fax: 508-852-8456

www.micronetworks.com

M2004-01

Preliminary Specifications

5

Micro Networks

An Integrated Circuit Systems Company

TABLE 4

PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Min

Typical

Max

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

kΩ

R

PULLDOWN

Input Pulldown Resistor

51

kΩ

TABLE 5B

PROGRAMMABLE VCSO FREQUENCY FUNCTION

VCSO Frequency

32

16

8421

(MHz)

M Divide

M5

M4

M3

M2

M1

M0

325

13

001101

350

14

001110

375

15

001111

400

16

0

1

0

0

0

0

••

••••••

••

••••••

600

24

011000

625

25

011001

650

26

011010

NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz.

TABLE 5A

PARALLEL & SERIAL MODES FUNCTION

Inputs

MR

nP Load

M

N

S Load S Clock S Data

Conditions

HX

XX

XX

X

Reset, Forces outputs LOW.

LL

Data

Data

X

X

X

Data on M and N inputs passed directly to the M

divider and N output divider. TEST output forced LOW.

L

↑

Data

Data

L

X

X

Data is latched into input registers and remains

loaded until next LOW transition or until a serial event

occurs.

LH

X

X

L

↑

Data

Serial input mode. Shift register is loaded with data

on S_DATA on each rising edge of S_CLOCK

LH

X

X

↑

LData

Contents of the shift register are passed to the M

divider and N output divider.

LH

X

X

↓

LDataM divider and N output divider values are latched.

LH

XX

LX

XParallel or serial input do not affect shift registers.

LH

X

X

H

↑

Data

S_DATA passed directly to M divider as it is clocked.

Note: L = Low; H = High; X = Don’t care; ↑ = Rising Edge Transition; ↓ = Falling Edge Transition