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TMS320AV7110 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320AV7110 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 131 page  DSP TMS320AV7110 Revision 3.1 10/08/99 22:18 Page 6 List of Figures FIGURE 1. THE ‘AV7110 BLOCK DIAGRAM.................................................................................................. 12 FIGURE 2. THE ‘AV7110 MEMORY MAP...................................................................................................... 13 FIGURE 3. SOFTWARE BLOCK DIAGRAM ........................................................................................................ 15 FIGURE 4. ARM CORE DATA PATH .............................................................................................................. 17 FIGURE 5. TRAFFIC CONTROLLER DATA FLOW ............................................................................................. 18 FIGURE 6. DEFAULT MEMORY ALLOCATION OF SDRAM (NTSC) ............................................................... 20 FIGURE 7. DEFAULT MEMORY ALLOCATION OF SDRAM (PAL).................................................................. 21 FIGURE 8. EXAMPLE CIRCUIT FOR 27 MHZ CLOCK GENERATION................................................................. 26 FIGURE 9. FEC INPUT INTERFACE TO TPP TIMING....................................................................................... 27 FIGURE 10: HARDWARE FILTER LAYOUT ........................................................................................................ 28 FIGURE 11. DISPLAY FORMATS FOR THE ‘AV7110 ....................................................................................... 36 FIGURE 12. OSD MODULE BLOCK DIAGRAM ............................................................................................... 42 FIGURE 13. USING THE OSD_ACTIVE SIGNAL FOR EXTERNAL ANALOG VIDEO ......................................... 45 FIGURE 14. OSD OUTPUT CHANNELS MATRIX............................................................................................. 46 FIGURE 15. EXTERNAL INSERTION OF TELETEXT SIGNAL.............................................................................. 49 FIGURE 16. DIGITAL VIDEO OUTPUT TIMING ................................................................................................. 50 FIGURE 17. PCM OUTPUT TIMING (16-BIT PCM FORMAT)........................................................................... 54 FIGURE 18. PTS TRACKING DIAGRAM........................................................................................................... 58 FIGURE 19. EXAMPLES OF DRAM CONNECTIONS TO 16-BIT AND 32-BIT EXTENSION BUSSES ....................... 63 FIGURE 20. BYTE ORDERING ON THE EXTENSION BUS .................................................................................. 64 FIGURE 21. FUNCTIONAL BLOCK DIAGRAM OF HIGH SPEED DATA INTERFACE............................................ 66 FIGURE 22. 1394 INTERFACE ........................................................................................................................ 66 FIGURE 23. 1394 INTERFACE READ SEQUENCE ............................................................................................ 68 FIGURE 24. 1394 INTERFACE WRITE SEQUENCE........................................................................................... 68 FIGURE 25. 1394 DATA FLOW BLOCK DIAGRAM .......................................................................................... 69 FIGURE 26. INTERFACING THE ‘AV7110 TO A SCSI CHIP ............................................................................. 70 FIGURE 27. PROGRAMMABLE DELAY FOR REGISTER ACCESSES ON THE EDMA PORT ................................. 71 FIGURE 28. PROGRAMMABLE DELAY FOR DMA ACCESSES ON THE EDMA PORT ........................................ 72 FIGURE 29. INTERFACING THE ‘AV7110 TO AN IEEE-1284 BUS................................................................... 72 FIGURE 30. COMBINED MPEG2LYNX, 1284 AND SCSI CONTROLLER .......................................................... 74 FIGURE 31. THE ‘AV7110’S INTERFACE TO TWO SMART CARDS ................................................................ 76 FIGURE 32. READ ACCESS FROM DRAM..................................................................................................... 109 FIGURE 33. WRITE ACCESS FROM DRAM ................................................................................................... 109 FIGURE 34. READ-MODIFY-WRITE ACCESS FOR 32 BIT DRAM .................................................................. 110 FIGURE 35. READ-MODIFY-WRITE ACCESS FOR 32 BIT DRAM .................................................................. 110 FIGURE 36. CAS BEFORE RAS DRAM REFRESH TIMING ........................................................................... 111 FIGURE 37. EXTENSION BUS SINGLE ACCESS READ TIMING (4 WAIT STATES)........................................... 111 FIGURE 38. EXTENSION BUS WRITE TIMING (4 WAIT STATES)................................................................... 112 FIGURE 39. EXTENSION BUS TIMING FOR MULTI-ACCESS MODE (3 WAIT STATES) .................................... 112 FIGURE 40. READ WITH EXTWAIT ACTIVE................................................................................................ 113 FIGURE 41. WRITE WITH EXTWAIT ACTIVE .............................................................................................. 114 FIGURE 42. SDRAM READ CYCLE ............................................................................................................. 115 FIGURE 43. SDRAM WRITE CYCLE ........................................................................................................... 116 FIGURE 44. SDRAM MULTI READ CYCLE.................................................................................................. 117 FIGURE 45. SDRAM MULTI WRITE CYCLE ................................................................................................ 118 FIGURE 46. SUCCESSIVE SDRAM OPERATIONS ......................................................................................... 119 FIGURE 47. VARIS CODE OUTPUT TIMING ................................................................................................ 121 FIGURE 48. DIGITAL VIDEO OUTPUT TIMING ............................................................................................... 122 FIGURE 49. 1394 READ CYCLE TIMING ...................................................................................................... 123 FIGURE 50. 1394 WRITE CYCLE TIMING...................................................................................................... 124 FIGURE 51. EXTERNAL DMA CYCLE TIMING .............................................................................................. 125 FIGURE 52. EXTERNAL DMA “REGISTER ACCESS” TIMING ........................................................................ 126 FIGURE 53. INPUT INTERFACE TIMINGS ...................................................................................................... 127 |
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