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LR36685 Datasheet(PDF) 2 Page - Sharp Corporation |
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LR36685 Datasheet(HTML) 2 Page - Sharp Corporation |
2 / 15 page 2 LZ23J3V PIN DESCRIPTION SYMBOL PIN NAME OD Output transistor drain OS Output signals ØRS Reset transistor clock ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 Vertical shift register clock ØH1, ØH2 Horizontal shift register clock PW P-well GND Ground NC No connection Overflow drain OFD ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C) PARAMETER SYMBOL RATING UNIT Output transistor drain voltage VOD 0 to +18 V Reset gate clock voltage VØRS Internal output V Vertical shift register clock voltage VØV VPW to +18 V Horizontal shift register clock voltage VØH –0.3 to +12 V Voltage difference between P-well and vertical clock VPW-VØV –29 to 0 V Storage temperature TSTG –40 to +85 ˚C Ambient operating temperature TOPR –20 to +70 ˚C 2 NOTE NOTES : 1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 33 Vp-p. 2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p. 3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 V. 1 V Internal output VOFD Overflow drain voltage 3 V 0 to +17 VØV-VØV Voltage difference between vertical clocks |
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