3

SP8647

L

H

L

H

PE1

L

L

H

H

TRUTH TABLE FOR

CONTROL INPUTS

11

10

10

10

PE2

Division ratio

Fig. 4 Timing diagram

Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 5V,

Ambient Temperature = 25

°C. Frequencies in MHz, impedances normalised to 50Ω.

OPERATING NOTES

1. The clock and control inputs are ECLIII compatible. There

and therefore any unused input can be left open circuit. If it

is desirable to capacitively couple the signal source to the

clock then an external bias is required as shown in Fig. 6.

The external bias voltage should be 21·3V at 25

°C.

2. The outputs are compatible with ECLII but can be interfaced

to ECL10K as shown in Fig.8.

3. The circuit will operate down to DC but slew rate must be

better than 100V/

µs.

4. Input impedance is a function of frequency. See Fig. 5.

5. The TTL/CMOS output is a free collector, with an output

rise/fall time which is a function of load resistance and load

capacitance. The load capacitance should therefore be kept

to a minimum and the load resistance should not be too

value of load resistor should be the maximum consistent

with satisfactory rise times.

6. All components should be suitable for the frequency in use.

6

5

5

CLOCK INPUT

PE INPUT

OUTPUT

j 2

j 1

j 0.5

j 0.2

0

2

j 0.2

2

j 0.5

2

j 1

2

j 2

1

0.5

0.2

j 5

2

j 5

2

5

50

100

150

200

250