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TLV320AIC31IRHBR Datasheet(PDF) 8 Page - Texas Instruments |
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TLV320AIC31IRHBR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 70 page  www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM ts(DI) th(DI) td(DO−BCLK) td(DO−WS) WCLK BCLK SDOUT SDIN td(WS) TIMING CHARACTERISTICS (1) ts(DI) th(DI) td(DO−BCLK) WCLK BCLK SDOUT SDIN td(WS) td(WS) TLV320AIC31 SLAS497 – DECEMBER 2005 Figure 2. I2S/LJF/RJF Timing in Master Mode All specifications typical at 25 °C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td (WS) ADWS/WCLK delay time 50 15 ns td (DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td BCLK to DOUT delay time 50 15 ns (DO-BCLK) ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns (1) All timing specifications are measured at characterization but not tested at final test. Figure 3. DSP Timing in Master Mode 8 |
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