F49L040A datasheet(7/41 Pages) ESMT

Part #	F49L040A

Description	4 Mbit (512K x 8) 3V Only CMOS Flash Memory

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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7 / 41 page

EFST

F49L040A

Elite Flash Storage Technology Inc.

Publication Date : Apr. 2005

Revision: 1.0

7/41

Figure 16 shows the algorithms and Figure 15 shows

the timing diagram. This method uses standard

microprocessor bus cycle timing. For sector unprotect,

all unprotected sectors must first be protected prior to

the first sector unprotect write cycle.

Auto-select Mode

The auto-select mode provides manufacturer and

device identification and sector protection verification,

through outputs on DQ7–DQ0. This mode is primarily

intended for programming equipment to automatically

match a device to be programmed with its

corresponding programming algorithm. However, the

auto-select codes can also be accessed in-system

through the command register.

When using programming equipment, this mode

requires VID (11.5 V to 12.5 V) on address pin A9.

While address pins A3, A2, A1, and A0 must be as

shown in Table 3.

To verify sector protection, all necessary pins have to

be set as required in Table 3, the programming

equipment may then read the corresponding identifier

code on DQ7-DQ0.

To access the auto-select codes in-system, the host

system can issue the auto-select command via the

command register, as shown in Table 4. This method

does not require VID. See “ Software Command

Definitions” for details on using the auto-select mode.

7.2 Software Command Definitions

Writing specific address and data commands or

sequences into the command register initiates the

device operations. Table 4 defines the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper sequence

resets the device to reading array data.

All addresses are latched on the falling edge of WE

or CE, whichever happens later. All data is latched on

the rising edge of WE or CE , whichever happens

first. Refer to the corresponding timing diagrams in

the AC Characteristics section.

Table 4. F49L040A Software Command Definitions

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Bus

Cycles

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset (5)

1

XXXH F0H

-

Read (4)

1

RA

RD

-

Program

4

555H

AAH 2AAH

55H

555H

A0H

PA

PD

Chip Erase

6

555H

AAH 2AAH

55H

555H

80H

555H

AAH 2AAH

55H

555H

10H

Sector Erase

6

555H

AAH 2AAH

55H

555H

80H

555H

AAH 2AAH

55H

SA

30H

Sector Erase

Suspend (6)

1

XXXH B0H

-

Sector Erase Resume

(7)

1

XXXH 30H

-

Auto-select

See Table 5.

Notes:

1. X = don’t care

RA = Address of memory location to be read.

RD = Data to be read at location RA.

PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address of the sector.

2. Except Read command and Auto-select command, all command bus cycles are write operations.

3. Address bits A18–A16 are don’t cares.

4. No command cycles required when reading array data.

5. The system may read and program in non-erasing sectors, or enter the auto-select mode, when in the Erase

Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

6. The Erase Resume command is valid only during the Erase Suspend mode.

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