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IDT7018L20PF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT7018L20PF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 17 page  6.42 IDT7018L High-Speed 64K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 9 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/ W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value. SEM 4841 drw 09 tAW tEW DATA0 VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT VALID(2) tDW tWP tDH tAS tSWRD tAOE tSOP Read Cycle Write Cycle A0-A2 OE tSOP SEM"A" 4841 drw 10 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE "B" (2) |
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