Electronic Components Datasheet Search |
|
DS1856B-020T Datasheet(PDF) 4 Page - Maxim Integrated Products |
|
DS1856B-020T Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 31 page Dual, Temperature-Controlled Resistors with Inter- nally Calibrated Monitors and Password Protection 4 _____________________________________________________________________ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 0 400 SCL Clock Frequency (Note 9) fSCL Standard mode 0 100 kHz Fast mode 1.3 Bus Free Time Between STOP and START Condition (Note 9) tBUF Standard mode 4.7 µs Fast mode 0.6 Hold Time (Repeated) START Condition (Notes 9, 10) tHD:STA Standard mode 4.0 µs Fast mode 1.3 LOW Period of SCL Clock (Note 9) tLOW Standard mode 4.7 µs Fast mode 0.6 HIGH Period of SCL Clock (Note 9) tHIGH Standard mode 4.0 µs Fast mode 0 0.9 Data Hold Time (Notes 9, 11, 12) tHD:DAT Standard mode 0 µs Fast mode 100 Data Setup Time (Note 9) tSU:DAT Standard mode 250 ns Fast mode 0.6 START Setup Time (Note 9) tSU:STA Standard mode 4.7 µs Fast mode 20 + 0.1CB 300 Rise Time of Both SDA and SCL Signals (Note 13) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 20 + 0.1CB 300 Fall Time of Both SDA and SCL Signals (Note 13) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6 Setup Time for STOP Condition tSU:STO Standard mode 4.0 µs Capacitive Load for Each Bus Line CB (Note 13) 400 pF EEPROM Write Time tW 10 20 ms AC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.) Note 1: All voltages are referenced to ground. Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. Note 3: SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels. Note 4: Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt- age on the inputs is greater than full scale. Note 5: This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage. Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a straight line from measured minimum position to measured maximum position. Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. Note 8: See the Typical Operating Characteristics. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. |
Similar Part No. - DS1856B-020T |
|
Similar Description - DS1856B-020T |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |