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M50FLW040BNB1T Datasheet(PDF) 11 Page - STMicroelectronics |
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M50FLW040BNB1T Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 52 page  11/52 M50FLW040A, M50FLW040B changed during Program or Erase Suspend, and care should be taken to avoid this. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being changed. When Write Protect, WP, is driven Low, VIL, Program and Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is driven High, VIH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 7). For details, see APPEN- DIX A.. Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must not be changed until the operation has completed other- wise unpredictable results may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or Erase Suspend, and care should be taken to avoid this. Reserved for Future Use (RFU). These pins do not presently have assigned functions. They must be left disconnected, except for ID3 (when in LPC mode) which can be left connected. The electrical characteristics for this signal are as described in the “Identification Inputs (ID0-ID3).” section. Address/Address Multiplexed (A/A Mux) Signal Descriptions Please see Figure 3. and Table 2.. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A18). They are latched during any bus operation by the Row/Col- umn Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data In- puts/Outputs hold the data that is to be written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they carry the commands that are sent to the Command In- terface of the internal state machine. The Data In- puts/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable signal, G, controls the output buffers during a Bus Read op- eration. Write Enable (W). The Write Enable signal, W, controls the Bus Write operation of the Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs are to be latched into the Row Ad- dress bits (A0-A10) or the Column Address bits (A11-A18). The Row Address bits are latched on the falling edge of RC whereas the Column Ad- dress bits are latched on its rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the device’s Program/Erase Controller. When Ready/Busy is Low, VOL, the de- vice is busy with a program or erase operation, and it will not accept any additional program or erase command (except for the Program/Erase Suspend command). When Ready/Busy is High, VOH, the memory is ready for any read, program or erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfac- es. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (read, pro- gram, erase, etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This is to prevent Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time, the operation aborts, and the memory contents that were being altered will be invalid. Af- ter VCC becomes valid, the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both VCC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents re- quired during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Pro- gram (see the Quadruple Byte Program command description in A/A Mux interface and the Double/ Quadruple Byte Program command description in FWH mode) and Fast Erase options of the memo- ry. When VPP = VCC, program and erase operations take place as normal. When VPP = VPPH, Fast Pro- gram and Erase operations are used. Any other voltage input to VPP will result in undefined behav- ior, and should not be used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the volt- age measurements. |
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