WM8200

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PP Rev 1.22 March 2002

11

CONTROL INTERFACE

The internal control registers are programmable via the 3-wire serial interface. SDIN is used for the

program data, SCLK is used to clock in the data and CSB is used to latch in the program data. The

3-wire interface protocol is shown in Figure 6.

Figure 6: 3-Wire Serial Interface

1.

A[3:0] are Control Address Bits

2.

D[7:0] are Control Data Bits

3.

CSB is edge sensitive – the data is latched on the rising edge of CSB.

REGISTER MAP

Table 3 shows the location of each control bit used to determine the operation of the WM8200. The

procedure for programming the register map is described in the CONTROL INTERFACE section.

BIT

ADDR

NAME

DEFAULT

(HEX)

B7

B6

B5

B4

B3

B2

B1

B0

0000

Clamp Reg 1

00

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

0001

Clamp Reg 2

00

0

0

0

0

0

0

DAC[9]

DAC[8]

0010

PGA Control

01

0

0

PGASENSE

PGAOFF

0

PGA[2]

PGA[1]

PGA[0]

0011

Control

00

0

0

0

CLPSEL

OEB

TWOSC

CLDIS

PD

0100 -

1111

Reserved

00

Reserved, do not write to these register locations

Table 3: Register Map

D7

D6

D5

D4

D3

D2

D1

D0

CSB

SCLK

SDIN

A3

A2

A1

A0

ADDRESS

DATA