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M50FLW040BN1TG Datasheet(PDF) 6 Page - STMicroelectronics |
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M50FLW040BN1TG Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 52 page  M50FLW040A, M50FLW040B 6/52 SUMMARY DESCRIPTION The M50FLW040 is a 4 Mbit (512Kb x8) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time. The memory is divided into 8 Uniform Blocks of 64 KBytes each, three of which are divided into 16 uniform sectors of 4 KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to pre- serve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents. Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set to control the memory is consistent with the JE- DEC standards. Two different bus interfaces are supported by the memory: s The primary interface, the FWH/LPC Interface, uses Intel’s proprietary Firmware Hub (FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets. The M50FLW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. s The secondary interface, the Address/ Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production line programming prior to fitting the device in a PC Motherboard. The memory is supplied with all the bits erased (set to ’1’). |
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