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FMS9884AKAC140 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FMS9884AKAC140 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 29 page  FMS9884A PRODUCT SPECIFICATION REV. 1.2.2 12/7/01 11 Figure 7. Output Timing PHASE N tDH tDO S0 D0 PXCK/XCK SC HSIN K RGBIN DCK HSOUT DCK D[7..0] Figures 13 through 21 depict data output timing relative to the sampling clock and inputs for all modes. Timing is refer- enced to the leading edge of HSIN when the first sample is taken at the rising edge of SCK. Status of register bit OUT- PHASE, determines if even samples are directed the A-port and odd samples are directed to the B-port; or vice versa. Note the timing of the HSOUT waveform: 1. HSOUT is always active HIGH. 2. Only the leading edge of HSOUT is active or selected by the HSPOL register bit. 3. HSOUT is aligned with DCK. 4. Trailing edge is linked to HSIN. 5. If HSIN does not terminate before mid-line, HSOUT is forced low. A 50% duty cycle indicates that HSPOL is incorrectly set. HS is the internal sync pulse generated from HSYNC. SCK is the internal A/D converter sampling clock. Output data transitions are synchronized with the falling edge of DCK. Output data should be strobed on the rising edge of DCK. A 5 to 6.5 clock cycle delay must be flushed before valid data is available. Alternate Pixel Sampling Mode A logic H on the CKINV pin inverts the sampling phase of SCK. In the Alternate Pixel Sampling Mode: 1. PLL is run at half rate. SCK, DCK and DCK are half rate. 2. CKINV is toggled between frames. (see Figure 18) VREFIN, with a nominal voltage of 1.25V, is the source of the differential reference voltages for each A/D converter. Reference voltages supplied to the differential inputs of the comparators in the A/D converters are derived from VREFIN. Digital Data Outputs Input horizontal sync, HSIN and outgoing data, D[7..0] are resynchronized to the delayed sample clock, SCK. Output timing characteristics are defined in Figure 7. Latency of the first pixel, N varies according to the mode: 1. Single or dual output port. 2. Interleaved or parallel output data. 3. 1-pixel or 2-pixel. Levels are 3.3 volt CMOS with the output supply variable between 2.5 and 3.3 V. PWRDN = L sets the outputs high-impedance. PWRDN = H enables the outputs. |
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