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LH540203K-25 Datasheet(PDF) 11 Page - Sharp Corporation |
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LH540203K-25 Datasheet(HTML) 11 Page - Sharp Corporation |
11 / 17 page TIMING DIAGRAMS tRS EFL t RSR t RRSS t WRSS t FFH t HFH t , RS R,W EF FF,HF 540203-14 tRSC NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ V IH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 10. Reset Timing W t WPW t RLZ t A t WC t A t RPW tDV t RHZ VALID DATA OUT tRR R tRC t WR t DH t DS VALID DATA IN 540203-5 Q0 - Q8 D0 - D8 VALID DATA OUT VALID DATA IN Figure 11. Asynchronous Write and Read Operation CMOS 2048 × 9 Asynchronous FIFO LH540203 11 |
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