CY28346-2
Document #: 38-07509 Rev. *A
Page 4 of 20
Byte 0: CPU Clock Register
Bit @Pup
Name
Description
7
0
Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
60
CPU clock Power-down Mode Select.
0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW.
1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to
CPU_STP#.
50
3V66_1/VCH
3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4
Pin 53
CPUT,CPUC
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only.
3Pin 34
PCI
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is
a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
2
Pin 40
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.
1
Pin 55
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.
0
Pin 54
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
Byte 1: CPU Clock Register
Bit @Pup
Name
Description
7
Pin 43
MULT0
MULT0 (Pin 43) Value. This bit is Read-only.
6
0
CPU_STP#
Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to
4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU
outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs
will be three-stated.
50
CPUT2
CPUC2
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
40
CPUT1
CPUC1
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
30
CPUT0
CPUC0
Controls CPUT0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
21
CPUT2
CPUC2
CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW
This is a Read and Write control bit.
11
CPUT1
CPUC1
CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW
This is a Read and Write control bit.
01
CPUT0
CPUC0
CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW
This is a Read and Write control bit.
Byte 2: PCI Clock Control Register (all bits are read and write functional)
Bit
@Pup
Name
Description
7
0
REF
REF Output Control. 0 = high strength, 1 = low strength
6
1
PCI6
PCI6 Output Control. 1 = enabled, 0 = forced LOW
5
1
PCI5
PCI5 Output Control. 1 = enabled, 0 = forced LOW
4
1
PCI4
PCI4 Output Control. 1 = enabled, 0 = forced LOW
3
1
PCI3
PCI3 Output Control. 1 = enabled, 0 = forced LOW
2
1
PCI2
PCI2 Output Control. 1 = enabled, 0 = forced LOW
1
1
PCI1
PCI1 Output Control. 1 = enabled, 0 = forced LOW
0
1
PCI0
PCI0 Output Control. 1 = enabled, 0 = forced LOW
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