AS7C33128PFD32A

AS7C33128PFD36A

®

3/22/01; v.1.0

Alliance Semiconductor

P. 2 of 11

Functional description

The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)

devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any

given technology.

frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller

address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst

addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data

accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by

asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented

internally to the next burst address if BWn and ADV are sampled Low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

•ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

•Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C33128PFD32A and AS7C33128PFD36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can

operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

Capacitance

Write enable truth table (per byte)

Key:

X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d;

Parameter

Symbol

Signals

Test conditions

Max

Unit

Input capacitance

Address and control pins

5

pF

I/O capacitance

I/O pins

7

pF

GWE

BWE

BWn

WEn

LX

X

T

HL

L

T

HH

X

F*

HLH