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XRT72L52 Datasheet(PDF) 3 Page - Exar Corporation |
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XRT72L52 Datasheet(HTML) 3 Page - Exar Corporation |
3 / 480 page áç áç áç áç XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY REV. P1.1.3 I TABLE OF CONTENTS GENERAL DESCRIPTION ............................................................................................... 1 FEATURES ................................................................................................................................................. 1 APPLICATIONS ........................................................................................................................................... 1 Figure 1. Block Diagram of the XRT72L52 ............................................................................................ 1 Figure 2. Pin Out of the XRT72L52 ........................................................................................................ 2 ORDERING INFORMATION ............................................................................................ 2 PIN DESCRIPTIONS ........................................................................................................ 3 ELECTRICAL CHARACTERISTICS .............................................................................. 24 ABSOLUTE MAXIMUMS ............................................................................................................................. 24 DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 24 AC ELECTRICAL CHARACTERISTICS ......................................................................................................... 24 AC ELECTRICAL CHARACTERISTICS (CONT.) ............................................................................................ 26 1.0 Timing Diagrams ................................................................................................................................. 30 Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L52 Device is operating in both the DS3 and Loop-Timing Modes ................................................................................................. 30 Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L52 Device is operating in both the DS3 and Local-Timing Modes ............................................................................................. 30 Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 Device is operating in both the DS3/Nibble and Looped-Timing Modes .............................................................. 31 Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 Device is operating in the DS3/Nibble and Local-Timing Modes .......................................................................... 31 Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 32 Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 32 Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the rising edge of "TxLineClk" ..................................................................................................................... 33 Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the falling edge of "TxLineClk" .................................................................................................................... 33 Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the rising edge of "RxLineClk" ..................................................................................................................... 34 Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the falling edge of "RxLineClk" .................................................................................................................... 34 Figure 13. Receive Payload Data Output Interface Timing .................................................................. 35 Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ......................... 35 Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ................ 36 Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 36 Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations .............. 37 Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations .............. 37 Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ..................... 38 Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation ....................... 38 Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 39 Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 39 Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........................................................ 40 2.0 The Microprocessor Interface Block ................................................................................................. 41 2.1 CHANNEL SELECTION WITHIN THE XRT72L52 DEVICE .......................................................................................... 41 TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS A(9) AND THE SELECTED CONFIGURATION REGISTER BANK ...................................................................................................................................................... 41 Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 42 2.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .............................................................................................. 42 TABLE 2: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND MOTOROLA MODES .......................................................................................................... 43 TABLE 3: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTER- FACE IS OPERATING IN THE INTEL MODE .................................................................................................. 43 |
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