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CY24206
Document #: 38-07451 Rev. *B
Page 3 of 6
Test and Measurement Set-up
Note:
1. Not 100% tested.
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
–0.5
7.0
V
VDDL
I/O Supply Voltage
7.0
V
TJ
Junction Temperature
125
°C
Digital Inputs
AVSS – 0.3
AVDD + 0.3
V
Electrostatic Discharge
2
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD/AVDDL/VDDL Operating Voltage
3.135
3.3
3.465
V
TA
Ambient Temperature
0
70
°C
CLOAD
Max. Load Capacitance
15
pF
fREF
Reference Frequency
27
MHz
DC Electrical Specifications
Parameter[1]
Name
Description
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD/VDDL = 3.3V
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD/VDDL = 3.3V
12
24
mA
IIH
Input High Current
VIH = VDD
–5
10
µA
IIL
Input Low Current
VIL = 0V
–
–
50
µA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
IVDD
Supply Current
AVDD/VDD Current
25
mA
IVDDL
Supply Current
VDDL Current
20
mA
RUP
Pull-up resistor on Inputs
VDD = 3.14 to 3.47V, measured VIN = 0V
100
150
k
Ω
AC Electrical Specifications
Parameter[1]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1; t1/t2, 50% of
VDD
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to
80% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80% to
20% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
t9
Clock Jitter
CLK1, CLK2 Peak-Peak period jitter
200
ps
t10
PLL Lock Time
3ms
0.1
µF
VDDs
Outputs
CLOAD
GND
DUT
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