Detailed Description

DC-to-DC PWM Controller

The MAX8529 step-down converter uses a PWM volt-

age-mode control scheme (Figure 2) for each out-of-

phase controller. The controller generates the clock

signal by dividing down the internal oscillator or SYNC

input when driven by an external clock, so each con-

troller’s switching frequency equals half the oscillator fre-

error amplifier produces an integrated error voltage at

the COMP pin, providing high DC accuracy. The voltage

at COMP sets the duty cycle using a PWM comparator

and a ramp generator. At each rising edge of the clock,

REG1’s high-side N-channel MOSFET turns on and

remains on until either the appropriate duty cycle or until

the maximum duty cycle is reached. REG2 operates out-

of-phase, so the second high-side MOSFET turns on at

each falling edge of the clock. During each high-side

MOSFET’s on-time, the associated inductor current

ramps up.

During the second-half of the switching cycle, the high-

side MOSFET turns off and the low-side N-channel

MOSFET turns on. Now the inductor releases the stored

energy as its current ramps down, providing current to

the output. Under overload conditions, when the induc-

tor current exceeds the selected valley current limit

(see the Current-Limit Circuit (ILIM_) section), the high-

side MOSFET does not turn on at the appropriate clock

edge and the low-side MOSFET remains on to let the

inductor current ramp down.

Synchronized Out-of-Phase Operation

The two independent regulators in the MAX8529 operate

180 degrees out-of-phase to reduce input filtering

requirements, reduce electromagnetic interference (EMI),

and improve efficiency. This effectively lowers component

cost and saves board space, making the MAX8529 ideal

for cost-sensitive applications.

Dual-switching regulators typically operate both

controllers in-phase, and turn on both high-side MOSFETs

at the same time. The input capacitor must then support

the instantaneous current requirements of both controllers

simultaneously, resulting in increased ripple voltage and

current when compared to a single switching regulator.

The higher RMS ripple current lowers efficiency due to

power loss associated with the input capacitor’s effective

series resistance (ESR). This typically requires more low-

ESR input capacitors in parallel to minimize input voltage

ripple and ESR-related losses, or to meet the necessary

ripple-current rating.

1.5MHz Dual 180° Out-of-Phase

PWM Step-Down Controller with POR

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7

Pin Description (continued)

PIN

NAME

FUNCTION

14

DH1

High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1.

15

LX1

External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the

inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.

16

BST1

Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic

capacitor and diode according to Figure 1.

17

DL1

18

PGND

Power Ground

19

Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers

and external boost circuitry for the high-side gate drivers.

20

DL2

21

BST2

Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic

capacitor and diode according to Figure 1.

22

LX2

External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the

inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.

23

DH2

High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2.

24

EN

operation.