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UPD160040AN-XXX Datasheet(PDF) 4 Page - NEC

Part # UPD160040AN-XXX
Description  384-OUTPUT TFT-LCD SOURCE DRIVER
Download  19 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
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UPD160040AN-XXX Datasheet(HTML) 4 Page - NEC

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Data Sheet S15918EJ1V0DS
4
µµµµPD160040A
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S1 to S384
Driver
Output
The D/A converted 256-gray-scale analog voltage is output.
D00 to D07
Port 1 display data
Input
The display data is input with a width of 48 bits, viz., the gray scale data
D10 to D17
(8 bits) by 6 dots (2 pixels).
D20 to D27
DX0: LSB, DX7: MSB
D30 to D37
Port 2 display data
Input
D40 to D47
D50 to D57
R,/L
Shift direction control
Input
The shift direction control pin of shift register. The shift directions of the
shift registers are as follows.
R,/L = H (right shift): STHR input
→S1→S384→STHL output
R,/L = L (left shift) : STHL input
→S384→S1→STHR output
STHR
Right shift start pulse
I/O
STHL
Left shift start pulse
I/O
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a high level is read at the rising
edge of CLK.
At the rising edge of the 64th clock after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of
the next-level driver.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
CLK
Shift clock
Input
The shift clock input pin of shift register. The display data is loaded into
the data register at the rising edge.
When 66 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage is
supplied to the driver. It is necessary to ensure input of one pulse per
horizontal period.
SRC
Slew-rate control
Input
SRC = H: High-slew-rate mode (large current consumption)
SRC = L: Low-slew-rate mode (small current consumption)
SRC is pulled up to the VDD1 in the IC.
ORC
Output resistance control
Input
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
ORC is pulled up to the VDD1 in the IC.
POL
Polarity
Input
POL = L: The S2n−1 output uses V0-V7 as the reference supply. The S2n
output uses V8-V15 as the reference supply.
POL = H: The S2n−1 output uses V8-V15 as the reference supply.
The S2n output uses V0-V7 as the reference supply.
S2n−1 indicates the odd output and S2n indicates the even output. Input
of the POL signal is allowed the setup time (tPOL–STB) with respect to
STB’s rising edge.
When it switches such as POL = H
→L or L→H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z (High impedance) during STB = H.
Refer to 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL
AND OUTPUT WAVEFORM for details.


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