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UPD160061NL Datasheet(PDF) 5 Page - NEC |
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UPD160061NL Datasheet(HTML) 5 Page - NEC |
5 / 18 page Data Sheet S15843EJ3V0DS 5 µPD160061 (2/2) Pin Symbol Pin Name I/O Description SRC High driving time control Input This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC. SRC = H or open: High drive time 64 CLK (Normally period mode) SRC = L: High drive time 128 CLK (Long time mode) Refer to 9. SRC AND HIGH DRIVE TIME. V0 to V9 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 7.5 to 9.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2,....., V9) and VSS. |
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