IDTCSPT857CPAGI datasheet(9/15 Pages) IDT

Part #	IDTCSPT857CPAGI

Description	2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

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Manufacturer	IDT [Integrated Device Technology]

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9

IDTCSPT857C

2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

SWITCHING CHARACTERISTICS FOR PC3200

Symbol

Description

Test Conditions

Min.

Typ.(1)

Max.

Unit

tPLH(1)

LOW to HIGH Level Propagation Delay Time

Test mode, CLK to any output

4.5

ns

tPHL(1)

HIGH to LOW Level Propagation Delay Time

Test mode, CLK to any output

4.5

ns

tJIT(PER)

Jitter(period),seefigure6

66MHz

– 90

90

ps

200 MHz

– 50

50

tJIT(CC)

Jitter(cycle-to-cycle),seefigure3

66MHz

–180

180

ps

200 MHz

– 75

75

tJIT(HPER)

Half-PeriodJitter,seefigure7

66MHz

–160

160

ps

200 MHz

– 75

75

tSLR(O)

OutputClockSlewRate(Single-Ended)

200 MHz (20% to 80%)

1

2.5

V/ns

tSLR(I)

Input Clock Slew Rate

1

4

V/ns

t(∅)

StaticPhaseOffset,seefigure4(2,3)

200 MHz

– 50

50

ps

tSK(O)

Output Skew, see figure 5

75

ps

tR,tF

Output Rise and Fall Times (20% to 80%)

Load: 120

Ω / 14pF

650

900

ps

VOX(5)

OutputDifferentialVoltage

Differentialoutputsareterminated

VDDQ/2

V

with 120

Ω

–0.15

+ 0.15

The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:

SSC

ModulationFrequency



30



50

KHz

SSC

ClockInputFrequencyDeviation



0



-0.5

%

f3dB

PLLLoopBandwidth



5



MHz

NOTES:

1. Refers to transition of non-inverting output.

2. Static phase offset does not include jitter.

3. t(

φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.

4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

5. VOX is specified at the SDRAM clock input or test load.

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IDTCSPT857CPAGI Datasheet(PDF) 9 Page - Integrated Device Technology

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