Electronic Components Datasheet Search |
|
IDT59920-7SO Datasheet(PDF) 2 Page - Integrated Device Technology |
|
IDT59920-7SO Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 6 page 2 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. PIN CONFIGURATION NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit Supply Voltage to Ground –0.5 to +7 V VI DC Input Voltage –0.5 to +7 V Maximum Power Dissipation (TA = 85°C) 530 mW TSTG Storage Temperature –65 to +150 °C NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested. CAPACITANCE(TA=+25°C,f=1MHz,VIN=0V) Parameter Description Typ. Max. Unit CIN InputCapacitance 5 7 pF PIN DESCRIPTION Pin Name Type Description REF IN ReferenceClockInput FB IN FeedbackInput TEST(1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. GND/ sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. VDDQ/PE IN Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedge ofthe referenceclock. FS(2) IN Frequency range select. 3 level input. FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VDD: 40 to 100MHz Q0 - Q7 OUT Eightclockoutput VDDN PWR Powersupplyforoutputbuffers VDDQ PWR Powersupplyforphase lockedloop and other internal circuitry GND PWR Ground NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF FS NC VDDQ/PE Q0 Q1 GND Q2 Q3 GND TEST NC GND/sOE Q7 Q6 GND Q5 Q4 FB VDDN VDDN VDDQ VDDN VDDN SOIC TOP VIEW |
Similar Part No. - IDT59920-7SO |
|
Similar Description - IDT59920-7SO |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |