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OR3T20-7S240 Datasheet(PDF) 7 Page - Agere Systems |
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OR3T20-7S240 Datasheet(HTML) 7 Page - Agere Systems |
7 / 210 page Lucent Technologies Inc. 7 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Description FPGA Overview The ORCA Series 3 FPGAs are a new generation of SRAM-based FPGAs built on the successful OR2C/ TxxA FPGA Series from Lucent Technologies Micro- electronics Group, with enhancements and innovations geared toward today’s high-speed designs and tomor- row’s systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA 2C/2T devices, Series 3 more than doubles the logic available in each logic block and incorporates sys- tem-level features that can further reduce logic require- ments and increase system speed. ORCA Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. The ORCA Series 3 FPGAs consist of three basic ele- ments: programmable logic cells (PLCs), programma- ble input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a sup- plemental logic and interconnect cell (SLIC), local rout- ing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be per- formed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the sys- tem-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM). PLC Logic Each PFU within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled indepen- dently. LUTs may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 sin- gle- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU out- puts make fast, true 3-state buses possible within the FPGA, reducing required routing and allowing for real- world system performance. |
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