T6L24

2002-01-07

5

Device Operation

(1) Analog signal sampling

Data transfer begins with the assertion of DI/O (U/D = high) or DO/I (U/D = low).

<Simultaneous sampling>

● When MODE

==== high, U/D ==== high

A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the

analog signal to be output to (SA1, SB1, SC1) is sampled at next rising edge of CPH. In this way, all

analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and

the analog signals are output to (SA2, SB2, SC2), (SA3, SB3, SC3) and so on.

After the device finishes sampling the data for (SA80, SB80, SC80), it automatically enters standby

state. Unless DI/O is asserted again, no data is sampled, irrespective of whether CPH are input to the

device.

● When MODE

==== high, U/D ==== low

A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the

analog signal to be output to (SA80, SB80, SC80) is sampled at next rising edge of CPH. In this way, all

analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and

the analog signals are output to (SA79, SB79, SC79), (SA78, SB78, SC78) and so on.

After the device finishes sampling the data for (SA1, SB1, SC1), it automatically enters standby state.

Unless DO/I is asserted again, no data is sampled, irrespective of whether CPH are input to the device.

<Sequential sampling>

● When MODE

==== low, U/D ==== high

A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the

analog signal to be output to SA1 is sampled at the rising edge of CPH after three clock period. In this

way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog

signals are output to SB1, SC1, SA2, SB2, SC2, SA3, SB3, SC3 and so on.

After the device finishes sampling the data for SC80, it automatically enters standby state. Unless DI/O

is asserted again, no data is sampled, irrespective of whether CPH are input to the device.

● When MODE

==== low, U/D ==== low

A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the

analog signal to be output to SC80 is sampled at the rising edge of CPH after three clock period. In this

way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog

signals are output to SB80, SA80, SC79, SB79, SA79, SC78, SB78, SA78 and so on.

After the device finishes sampling the data for SA1, it automatically enters standby state. Unless DO/I

is asserted again, no data is sampled, irrespective of whether CPH are input to the device.