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MC100ES6221 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MC100ES6221 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 12 page Advanced Clock Drivers Devices 6 Freescale Semiconductor MC100ES6221 Table 7. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or (PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to + 110°C)(1) 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLK0, CLK0 (PECL or ECL differential signals) VPP Differential Input Voltage(2) (peak-to-peak) 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 0.2 1.3 V VCMR Differential Input Crosspoint Voltage(3) PECL ECL 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 1.0 VEE + 1.0 VCC – 0.3 –0.3 V V V fCLK Input Frequency 0 2000 MHz Differential tPD Propagation Delay CLK0 to Q0-19 400 540 670 ps Differential Clock Input Pair CLK1, CLK1 (HSTL differential signals) VDIF Differential Input Voltage(4) (peak-to-peak) 4. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. Only applicable to CLKB. 0.2 1.3 V VX Differential Input Crosspoint Voltage(5) 5. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 0.1 0.68–0.9 VCC – 1.0 V fCLK Input Frequency 0 1000 MHz Differential tPD Propagation Delay CLK1 to Q0–19 650 780 950 ps Differential PECL/ECL Clock Outputs (Q0–19, Q0–19) VO(P-P) Differential Output Voltage (peak-to-peak) fO < 1.0 GHz fO < 2.0 GHz 0.375 TDB 0.630 0.250 V V tsk(O) Output-to-Output Skew 50 100 ps Differential tsk(PP) Output-to-Output Skew (part-to-part) using CLK0 using CLK1 parts at one given TJ, VCC, fref 270 300 250 ps ps ps Differential tJIT(CC) Output Cycle-to-Cycle Jitter RMS (1 σ)1 ps tSK(P) DCQ Output Pulse Skew(6) Output Duty Cycle fREF < 0.1 GHz fREF < 1.0 GHz 6. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |. 49.5 45.0 30 50 50 50 50.5 55.0 ps % % DCREF = 50% DCREF = 50% tr, tf Output Rise/Fall Time 50 350 ps 20% to 80% |
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