NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Preliminary, 11/2001
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0 , CK1, CK2
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.
CK0 , CK1 , CK2
(SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
CKE0, CKE1
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
S0 , S1
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
RAS
, CAS , WE
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock, RAS
, CAS , WE define the
operation to be executed by the SDRAM.
VREF
Supply
Reference voltage for SSTL-2 inputs
VDDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1
(SSTL)
-
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11
(SSTL)
-
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63,
(SSTL)
-
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQS0 - DQS7
DQS9 - DQS16
(SSTL)
Active
High
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
VDD , VSS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
SA0 – SA2
-
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pullup.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pullup.
VDDSPD
Supply
Serial EEPROM positive power supply.
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