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NT512D64S8HB0G Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers

Part # NT512D64S8HB0G
Description  184 pin Unbuffered DDR DIMM
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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NT512D64S8HB0G Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers

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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
REV 2.2
10
Aug 3, 2004
Preliminary
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect
SPD Description
Byte
Description
Byte
Description
0
Number of Serial PD Bytes Written during Production
26
Maximum Data Access Time from Clock at CL=1
1
Total Number of Bytes in Serial PD device
27
Minimum Row Precharge Time (tRP)
2
Fundamental Memory Type
28
Minimum Row Active to Row Active delay (tRRD)
3
Number of Row Addresses on Assembly
29
Minimum RAS to CAS delay (tRCD)
4
Number of Column Addresses on Assembly
30
Minimum RAS Pulse Width (tRAS)
5
Number of DIMM Rank
31
Module Bank Density
6
Data Width of Assembly
32
Address and Command Setup Time Before Clock
7
Data Width of Assembly (cont’)
33
Address and Command Hold Time After Clock
8
Voltage Interface Level of this Assembly
34
Data Input Setup Time Before Clock
9
DDR SDRAM Device Cycle Time
CL=2.5
35
Data Input Hold Time After Clock
10
DDR SDRAM Device Access Time from Clock
CL=2.5
36-40
Reserved
11
DIMM Configuration Type
41
Minimum Active/Auto-refresh Time (tRC)
12
Refresh Rate/Type
42
Auto-refresh to Active/Auto-refresh Command Period
(tRFC)
13
Primary DDR SDRAM Width
43
Max Cycle Time (tCK max)
14
Error Checking DDR SDRAM Device Width
44
Maximum DQS-DQ Skew Time (tDQSQ)
15
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
45
Maximum Read Data Hold Skew Factor (tQHS)
16
DDR SDRAM Device Attributes: Burst Length
Supported
46-61
Reserved
17
DDR SDRAM Device Attributes: Number of Device
Banks
62
SPD Revision
18
DDR SDRAM Device Attributes:
CAS Latencies Supported
63
Checksum Data
19
DDR SDRAM Device Attributes: CS Latency
64-71
Manufacturer’s JEDEC ID Code
20
DDR SDRAM Device Attributes: WE Latency
72
Module Manufacturing Location
21
DDR SDRAM Device Attributes:
73-90
Module Part number
22
DDR SDRAM Device Attributes: General
91-92
Module Revision Code
23
Minimum Clock Cycle
CL=2.5
93-94
Module Manufacturing Data
yy= Binary coded decimal year code, 0-99(Decimal),
00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal),
01-34(Hex)
24
Maximum Data Access Time from Clock at
CL=2
95-98
Module Serial Number
25
Minimum Clock Cycle Time at CL=1
99-127
Reserved


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