V96BMC Rev.D
4
V96BMC Rev D Data Sheet Rev 3.2
Copyright © 1998, V3 Semiconductor Inc.
Signal
Type
R
Description
A[31:2]
I
Local address bus.
ALE
I
Address Latch Enable: controls a set of transparent latches on the
address bus. When asserted high, the address input flows through
the latch. When ALE is low, the internal address holds the previous
value. With an i960Cx/Hx processor ALE is not typically used and
has an internal pull-up resistor that will keep it high when not con-
nected (to provide backward pin compatibility with earlier versions).
D/C
I
Data/Code.
BE[3:0]
I
Local bus byte write enables.
W/R
IWrite/Read.
READY
O12
Z
Local Bus data ready.
ADS
I
Asserted low to indicate the beginning of a bus cycle
DEN
I
Data Enable. This input is monitored by the Bus Watch Timer to
detect a bus access not returning READY.
SUP
I
Indicates supervisor mode. Required for access to configuration reg-
isters.
BLAST
I
Burst last.
BTERM
O12
Z
Burst terminate. (this signal requires a nominal pull up resistor so
that the signal is deasserted when RESET goes inactive)
BERR
O12
H
Bus Time-out error.
INT
O12
H
Local interrupt request. This signal is asserted when the 24-bit
counter reaches terminal count, and interrupt out is enabled. May
be programmed for pulse or level operation.
RESET
I
Local bus reset signal.
PCLK
I
Local bus clock.
ID[2:0]
I
These inputs select the address offset of the configuration registers.
Power and Ground Signals
Signal
Type
R
Description
Vcc
-
POWER leads intended for external connection to a 5V Vcc plane
Vcc3
-
POWER for DRAM control outputs. Can be connected to 3.3V or 5V.
GND
-
GROUND leads intended for external connection to a GND plane.
a. R indicates state during reset.
Table 3: Signal Descriptions (cont’d)
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