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PMWD26UN Datasheet(PDF) 2 Page - NXP Semiconductors |
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PMWD26UN Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page 9397 750 14982 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 19 May 2005 2 of 12 Philips Semiconductors PMWD26UN Dual N-channel µTrenchMOS ultra low level FET 3. Ordering information 4. Limiting values [1] Single device conducting. Table 2: Ordering information Type number Package Name Description Version PMWD26UN TSSOP8 plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ T j ≤ 150 °C - 20 V VDGR drain-gate voltage (DC) 25 °C ≤ T j ≤ 150 °C; RGS =20kΩ -20 V VGS gate-source voltage - ±10 V ID drain current (DC) Tsp =25 °C; VGS = 4.5 V; Figure 2 and 3 [1] - 7.8 A Tsp = 100 °C; VGS = 4.5 V; Figure 2 [1] - 4.7 A IDM peak drain current Tsp =25 °C; pulsed; tp ≤ 10 µs; Figure 3 [1] - 31.3 A Ptot total power dissipation Tsp =25 °C; Figure 1 [1] - 3.1 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp =25 °C - 2.6 A ISM peak source (diode forward) current Tsp =25 °C; pulsed; tp ≤ 10 µs - 10.3 A |
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