COMMERCIAL TEMPERATURE RANGE

SEPTEMBER 1998

©1998 Integrated Device Technology, Inc

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Integrated Device Technology, Inc.

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Choose among the following memory organizations:

IDT72275

32,768 x 18

IDT72285

65,536 x 18

• Pin-compatible with the IDT72255LA/72265LA SuperSync

FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

EF and FF flags) or First

Word Fall Through timing (using

OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and

writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the

64-pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

DESCRIPTION:

The IDT72275/72285 are exceptionally deep, high speed,

CMOS First-In-First-Out (FIFO) memories with clocked read

and write controls. These FIFOs offer numerous improve-

ments over previous SuperSync FIFOs, including the following:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency

Select pin (FS) has been removed, thus it is no longer

necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

• The first word data latency period, from the time the first

word is written to an empty FIFO to the time it can be read,

is now fixed and short. (The variable clock cycle counting

FUNCTIONAL BLOCK DIAGRAM

PRELIMINARY

IDT72275

IDT72285

CMOS SUPERSYNC FIFO™

32,768 x 18

65,536 x 18

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

32,768 x 18

65,536 x 18

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WCLK

RCLK

OFFSET REGISTER

FWFT/SI

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For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.