Preliminary

Rev 4.0

K7P801811B

256Kx36 & 512Kx18 SRAM

K7P803611B

Aug. 2002

- 2 -

PIN DESCRIPTION

Pin Name

Pin Description

Pin Name

Pin Description

K, K

Differential Clocks

ZZ

Asynchronous Power Down

SAn

Synchronous Address Input

ZQ

Output Driver Impedance Control

DQn

Bi-directional Data Bus

TCK

JTAG Test Clock

SS

Synchronous Select

TMS

JTAG Test Mode Select

SW

Synchronous Global Write Enable

TDI

JTAG Test Data Input

SWa

Synchronous Byte a Write Enable

TDO

JTAG Test Data Output

SWb

Synchronous Byte b Write Enable

HSTL Input Reference Voltage

SWc

Synchronous Byte c Write Enable

Power Supply

SWd

Synchronous Byte d Write Enable

Output Power Supply

GND

G

Asynchronous Output Enable

NC

No Connection

256Kx36 & 512Kx18 Synchronous Pipelined SRAM

FEATURES

FUNCTIONAL BLOCK DIAGRAM

18 or 19

K,K

SS

G

Memory Array

256Kx36

Data Out

Data In

S/A Array

MUX0

W/D

Array

36 or 18

36 or 18

36 or 18

36 or 18

2:1

MUX

Dec.

SA[0:17]

Address

Register

Read

SW

ZZ

Internal

Clock

Generator

Write

Address

Register

Data Out

Register

Clock

Buffer

Control

Register

DQ

36 or 18

36 or 18

36 or 18

36 or 18

XDIN

Data In

Register

(2 stage)

18 or 19

Control

Logic

E

WAY

OE

36 or 18

or [0:18]

512Kx18

Organization

Part Number

Maximum

Frequency

Access

Time

256Kx36

K7P803611B-HC33

333MHz

1.5

K7P803611B-HC30

300MHz

1.6

K7P803611B-HC27

250MHz

1.85

K7P803611B-HC25

250MHz

2.0

512Kx18

K7P801811B-HC33

333MHz

1.5

K7P801811B-HC30

300MHz

1.6

K7P801811B-HC27

300MHz

1.85

K7P801811B-HC25

250MHz

2.0

• 256Kx36 or 512Kx18 Organizations.

• HSTL Input and Output Levels.

• Differential, HSTL Clock Inputs K, K.

• Synchronous Read and Write Operation

• Registered Input and Registered Output

• Internal Pipeline Latches to Support Late Write.

• Byte Write Capability(four byte write selects, one for each 9bits)

• Synchronous or Asynchronous Output Enable.

• Power Down Mode via ZZ Signal.

• Programmable Impedance Output Drivers.

• JTAG Boundary Scan (subset of IEEE std. 1149.1).

• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).