SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A

DUAL 4-BIT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SDAS036D – APRIL 1982 – REVISED AUGUST 1995

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

tPHZ

tPLZ

tPHL

tPLH

0.3 V

tPZL

tPZH

TEST

S1

Open

Open

Open

tPHL

tPZH

tPZL

Closed

Open

Closed

tPHZ

tPLZ

tPLH

tPHL

LOAD CIRCUIT FOR 3-STATE OUTPUTS

From Output

Under Test

Test Point

R1 = 500

Ω

S1

CL = 50 pF

(see Note A)

7 V

Open

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

Out-of-Phase

Output

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

VOL

VOH

VOH

VOL

Output

Control

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

0 V

VOH

VOL

3.5 V

In-Phase

Output

0.3 V

tPLH

1.3 V

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

SWITCH POSITION TABLE

R2 = 500

Ω

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms