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XRT83SL30 Datasheet(PDF) 8 Page - Exar Corporation |
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XRT83SL30 Datasheet(HTML) 8 Page - Exar Corporation |
8 / 76 page XRT83SL30 áç áç áç áç SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.0.4 PRELIMINARY 5 RECEIVER SIGNAL NAME PIN #TYPE DESCRIPTION RLOS 63 O Receiver Loss of Signal This signal is asserted ‘High’ for at least one RCLK cycle to indicate loss of signal at the receive input. RLOS will remain “High” for the entire duration of the loss of signal detected by the receiver logic. RCLK 64 O Receiver Clock Output RNEG LCV 1 O Receiver Negative Data Output In dual-rail mode, this signal is the receiver negative-rail output data. Line Code Violation Output In single-rail mode, this signal goes ‘High’ for one RCLK cycle to indicate a code violation is detected in the received data. If AMI coding is selected, every bipolar violation received will cause this pin to go “High”. RPOS RDATA 2 O Receiver Positive Data Output In dual-rail mode, this signal is the receive positive-rail output data sent to the Framer. Receiver NRZ Data Output In single-rail mode, this signal is the receive NRZ format output data sent to the Framer. RTIP 4 I Receiver Differential Tip Positive Input Positive differential receive input from the line. RRING 5 I Receiver Differential Ring Negative Input Negative differential receive input from the line. RXMUTE 50 I Receive Muting In Hardware Mode, connect this pin ‘High’ to mute RPOS and RNEG out- puts to a “Low” state upon receipt of LOS condition to prevent data chatter- ing. Connect this pin to ‘Low’ to disable muting function. NOTE: Internally pulled “Low” with 50k Ω resistor. RCLKE 53 I Receive Clock Edge In Hardware Mode, with this pin set to ‘High’ the output receive data is updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is updated on the rising edge of RCLK. NOTE: Internally pulled “Low” with a 50k Ω resistor. |
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