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XRT83SL30 Datasheet(PDF) 1 Page - Exar Corporation |
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XRT83SL30 Datasheet(HTML) 1 Page - Exar Corporation |
1 / 76 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç áç áç áç PRELIMINARY XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MAY 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT83SL30 is a fully integrated single-channel short-haul line interface unit for T1(1.544Mbps) 100 Ω, E1(2.048Mbps) 75 Ω or 120Ω and J1 110Ω applica- tions. In T1 applications, the XRT83SL30 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements. The XRT83SL30 provides both Serial Host micropro- cessor interface and Hardware Mode for program- ming and control. Both B8ZS and HDB3 encoding and decoding functions are included and can be dis- abled as required. On-chip crystal-less jitter attenua- tor with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83SL30 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75 Ω, 100Ω, 110Ω and 120Ω for both transmitter and receiver. For the receiver this is accomplished with internal resistors or through the combination of one single fixed value external resistor and program- mable internal resistors. In the absence of the power supply, the transmit output and receive input are tri- stated allowing for redundancy applications. The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a va- riety of external clock sources. APPLICATIONS • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks FEATURES (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE) HW/HOST CS INT ICT TPOS / TDATA TNEG / CODES TCLK QRPD RCLK RNEG / LCV RPOS / RDATA NLCD RLOS RTIP RRING MASTER CLOCK SYNTHESIZER QRSS PATTERN GENERATOR DMO TTIP TRING TXON HDB3/ B8ZS ENCODER TX/RX JITTER ATTENUATOR TIMING CONTROL TX FILTER & PULSE SHAPER LINE DRIVER DRIVE MONITOR LOCAL ANALOG LOOPBACK REMOTE LOOPBACK DIGITAL LOOPBACK HDB3/ B8ZS DECODER TX/RX JITTER ATTENUATOR TIMING & DATA RECOVERY PEAK DETECTOR & SLICER QRSS DETECTOR NETWORK LOOP DETECTOR RX EQUALIZER EQUALIZER CONTROL AIS DETECTOR LOS DETECTOR LBO[3:0] LOOPBACK ENABLE NLCD ENABLE QRSS ENABLE SDO SCLK SDI RESET Serial Interface TEST TAOS ENABLE MCLKE1 MCLKT1 MCLKOUT AISD |
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