 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PI7C8148ANJ Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation |
|
||||||||||||||||||||||||||||||
PI7C8148ANJ Datasheet(HTML) 5 Page - Pericom Semiconductor Corporation |
|
|
5 / 90 page  PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 5 of 90 JUNE 2004 – Revision 1.04 TABLE OF CONTENTS 1 SIGNAL DEFINITIONS.............................................................................................................................13 1.1 SIGNAL TYPES....................................................................................................................................13 1.2 SIGNALS ..............................................................................................................................................13 1.2.1 PRIMARY BUS INTERFACE SIGNALS ...................................................................................13 1.2.2 SECONDARY BUS INTERFACE SIGNALS .............................................................................14 1.2.3 CLOCK SIGNALS ........................................................................................................................16 1.2.4 MISCELLANEOUS SIGNALS ....................................................................................................16 1.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS .................................................................17 1.2.6 POWER AND GROUND..............................................................................................................17 1.3 PIN LIST – 160-PIN LFBGA.................................................................................................................18 2 PCI BUS OPERATION...............................................................................................................................19 2.1 TYPES OF TRANSACTIONS ..............................................................................................................19 2.2 SINGLE ADDRESS PHASE.................................................................................................................20 2.3 DEVICE SELECT (DEVSEL#) GENERATION ..................................................................................20 2.4 DATA PHASE.......................................................................................................................................20 2.5 WRITE TRANSACTIONS....................................................................................................................20 2.5.1 MEMORY WRITE TRANSACTIONS.........................................................................................21 2.5.2 MEMORY WRITE AND INVALIDATE .....................................................................................22 2.5.3 DELAYED WRITE TRANSACTIONS ........................................................................................22 2.5.4 WRITE TRANSACTION BOUNDARIES...................................................................................23 2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................23 2.5.6 FAST BACK-TO-BACK TRANSACTIONS ................................................................................23 2.6 READ TRANSACTIONS .....................................................................................................................24 2.6.1 PREFETCHABLE READ TRANSACTIONS.............................................................................24 2.6.2 DYNAMIC PREFETCHING CONTROL....................................................................................24 2.6.3 NON-PREFETCHABLE READ TRANSACTIONS ...................................................................24 2.6.4 READ PREFETCH ADDRESS BOUNDARIES ........................................................................25 2.6.5 DELAYED READ REQUESTS ...................................................................................................25 2.6.6 DELAYED READ COMPLETION WITH TARGET .................................................................26 2.6.7 DELAYED READ COMPLETION ON INITIATOR BUS.........................................................26 2.6.8 FAST BACK-TO-BACK READ TRANSACTIONS ....................................................................27 2.7 CONFIGURATION TRANSACTIONS................................................................................................27 2.7.1 TYPE 0 ACCESS TO PI7C8148A................................................................................................28 2.7.2 TYPE 1 TO TYPE 0 CONVERSION ...........................................................................................28 2.7.3 TYPE 1 TO TYPE 1 FORWARDING ..........................................................................................29 2.7.4 SPECIAL CYCLES.......................................................................................................................30 2.8 TRANSACTION TERMINATION.......................................................................................................30 2.8.1 MASTER TERMINATION INITIATED BY PI7C8148A ..........................................................31 2.8.2 MASTER ABORT RECEIVED BY PI7C8148A .........................................................................32 2.8.3 TARGET TERMINATION RECEIVED BY PI7C8148A ...........................................................32 2.8.4 TARGET TERMINATION INITIATED BY PI7C8148A...........................................................34 3 ADDRESS DECODING..............................................................................................................................36 3.1 ADDRESS RANGES ............................................................................................................................36 3.2 I/O ADDRESS DECODING..................................................................................................................36 3.2.1 I/O BASE AND LIMIT ADDRESS REGISTER .........................................................................37 3.2.2 ISA MODE ....................................................................................................................................37 3.3 MEMORY ADDRESS DECODING.....................................................................................................38 3.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..................................38 3.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..........................39 |
Similar Part No. - PI7C8148ANJ |
|
Similar Description - PI7C8148ANJ |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
