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PI7C8148ANJ Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI7C8148ANJ Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
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7 / 90 page  PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 7 of 90 JUNE 2004 – Revision 1.04 14 BRIDGE BEHAVIOR.............................................................................................................................62 14.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES.........................................................................62 14.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ..............................................63 14.2.1 MASTER ABORT.........................................................................................................................63 14.2.2 PARITY AND ERROR REPORTING .........................................................................................63 14.2.3 REPORTING PARITY ERRORS.................................................................................................63 14.2.4 SECONDARY IDSEL MAPPING................................................................................................63 15 CONFIGURATION REGISTERS.........................................................................................................64 15.1 REGISTER TYPES ...............................................................................................................................64 15.2 CONFIGURATION REGISTER...........................................................................................................64 15.2.1 VENDOR ID REGISTER – OFFSET 00h ..................................................................................65 15.2.2 DEVICE ID REGISTER – OFFSET 00h....................................................................................65 15.2.3 COMMAND REGISTER – OFFSET 04h ...................................................................................65 15.2.4 PRIMARY STATUS REGISTER – OFFSET 04h ......................................................................66 15.2.5 REVISION ID REGISTER – OFFSET 08h................................................................................67 15.2.6 CLASS CODE REGISTER – OFFSET 08h................................................................................67 15.2.7 CACHE LINE REGISTER – OFFSET 0Ch ...............................................................................67 15.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.....................................................67 15.2.9 HEADER TYPE REGISTER – OFFSET 0Ch ............................................................................67 15.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h .......................................................67 15.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................68 15.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................68 15.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...........................................68 15.2.14 I/O BASE ADDRESS REGISTER – OFFSET 1Ch................................................................68 15.2.15 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ..............................................................68 15.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch............................................................69 15.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h ....................................................69 15.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ...................................................70 15.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h....................70 15.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..................70 15.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ...................................................................................................................................................70 15.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ...................................................................................................................................................71 15.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ...................................71 15.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ..................................71 15.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ..........................................................71 15.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch ..................................................................71 15.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch .....................................................................71 15.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................72 15.2.29 DIAGNOSTIC/CHIP CONTROL REGISTER – OFFSET 40h .............................................73 15.2.30 ARBITER CONTROL REGISTER – OFFSET 40h ...............................................................74 15.2.31 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h ................................................74 15.2.32 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch ..75 15.2.33 P_SERR# EVENT DISABLE REGISTER – OFFSET 64h ...................................................76 15.2.34 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ..........................................77 15.2.35 P_SERR# STATUS REGISTER – OFFSET 68h....................................................................77 15.2.36 CLKRUN REGISTER – OFFSET 6Ch ...................................................................................78 15.2.37 PORT OPTION REGISTER – OFFSET 74h..........................................................................78 15.2.38 CAPABILITY ID REGISTER – OFFSET 80h .......................................................................80 15.2.39 NEXT ITEM POINTER REGISTER – OFFSET 80h ............................................................80 15.2.40 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................81 |
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