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XPC850CZT80B Datasheet(PDF) 6 Page - Motorola, Inc |
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XPC850CZT80B Datasheet(HTML) 6 Page - Motorola, Inc |
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6 / 76 page  6 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk® — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) • QUICC multichannel controller (QMC) microcode features — Up to 64 independent communication channels on a single SCC — Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots — Supports either transparent or HDLC protocols for each channel — Independent TxBDs/Rx and event/interrupt reporting for each channel • One universal serial bus controller (USB) — Supports host controller and slave modes at 1.5 Mbps and 12 Mbps • Two serial management controllers (SMCs) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division-multiplexed (TDM) channel • One serial peripheral interface (SPI) — Supports master and slave modes — Supports multimaster operation on the same bus • One I2C® (interprocessor-integrated circuit) port — Supports master and slave modes — Supports multimaster environment • Time slot assigner — Allows SCCs and SMCs to run in multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame syncs, clocking — Allows dynamic changes — Can be internally connected to four serial channels (two SCCs and two SMCs) • Low-power support |
Similar Part No. - XPC850CZT80B |
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Similar Description - XPC850CZT80B |
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